The following will explain an active matrix display device as an example of a conventional image display device.
As shown in FIG. 11, the image display device is made up of a pixel array 51, a scanning signal line driving circuit 52 and a data signal line driving circuit 53. The pixel array 51 includes a plurality of scanning signal lines GL1, GL2, . . . GLy and a plurality of data signal lines SL1, SL2, . . . SLx, which are provided by crossing each other. Also, pixels 54 are provided in a matrix manner on the pixel array 51 between two adjacent scanning signal lines GLy-1 and GLy, and two adjacent data signal lines SLx-1 and SLx.
The data signal line driving circuit 53 samples an inputted image signal DAT in synchronism with a timing signal such as a source clock signal SCK, and amplifies the image signal if necessary, then write the signal to the data signal lines SL1, SL2, . . . SLx.
The scanning signal line driving circuit 52 sequentially selects the scanning signal lines GL1, GL2, . . . GLy in synchronism with a timing signal such as a gate clock signal GCK, and write the image signal DAT thus written on the data signal lines SL1, SL2, . . . SLx to the pixels 54 by turning on/off switching element (not shown) in the pixels 54, and holds the image signal DAT written in a memory in the pixels 54.
Incidentally, in a conventional active matrix display device, the data signal line driving circuit 53 and the scanning signal line driving circuit 52 are generally provided as external ICs (Integrated Circuits), as shown in FIG. 11. However, in recent years, a new technique has been revealed such as the arrangement of FIG. 12 such that a pixel array 61, a data signal line driving circuit 63 and a scanning signal line driving circuit 62 are monolithically formed on a single insulating substrate 65. Further, a control circuit 66 for supplying various signals and a power supply circuit 67 are connected to the driving circuits 62 and 63.
Here, in the conventional active matrix display device, the following will explain an arrangement example of the scanning signal line driving circuit 62 which drives the scanning signal lines GL1, GL2, . . . GLy, and also explain the driving method thereof.
As shown in FIG. 13, a common scanning signal line driving circuit 62 is made up of a plurality of shift registers SR1 through SRn, waveform shaping circuits PP1 through PPn and buffer circuits 71. The plurality of shift registers SR1 through SRn sequentially shift active state of externally inputted gate start pulse signal GSP in synchronism with a gate clock signal GCK and its inversion signal GCKB, which are also externally inputted. The waveform shaping circuits PP1 through PPn shape the waveforms outputted from the shift registers SR1 through SRn to desired shapes. The buffer circuits 71 transmit the outputs from the waveform shaping circuits PP1 through PPn to the scanning signal lines GL1, GL2, . . . GLn.
FIG. 14 shows the timing waveform of the scanning signal line driving circuit 62 having the foregoing arrangement. As shown in the figure, the active state of the gate start pulse signal GSP is sequentially shifted in synchronism with the gate clock pulse signal GCK, and outputted as output signals SRO1, SRO2, . . . SROn of the shift registers SR1 through SRn. Then, these output signal SRO1, SRO2, . . . SROn of the shift registers SR1 through SRn are outputted as output signals GO1 through GOn by being shaped and shortened in wave width by each of the waveform shaping circuits PP1 through PPn so as to be. Further, these outputted signals GO1 through GOn are inputted to the buffer circuits 71, and then are outputted as actual driving waveforms of the scanning signal lines GL1, GL2, . . . GLn.
Generally, each of the shift registers SR1 through SRn provides vertical resolution corresponding to the number of the scanning signal lines GL1, GL2, . . . GLy. Therefore, the scanning signal lines GL1, GL2, . . . GLn are individually driven at different timings by the shift registers SR1 through SRn so as to respectively write an individual image signal DAT on the pixels 64 connected to scanning signal lines GL1 through GLy shown in FIG. 12 in a parallel direction to the data signal lines SL1, SL2, . . . SLx. This is a physical display resolution of the maximum value in a vertical direction of the image display device and makes it possible to carry out display close to an image source as much as possible when the inputted image signal DAT has the same level of vertical resolution or greater.
On the other hand, when the inputted image signal DAT has vertical resolution lower than the maximum physical display resolution in a vertical direction of the image display device, for example, in the case of displaying an image signal of SVGA (800 (horizontal)×600 (vertical) pixels) with an image display device having a maximum physical display resolution of UXGA (1600 (horizontal)×1200 (vertical) pixels), generally, a method which sequentially drives a plurality of adjacent scanning signal lines GLy−1 and GLy is adopted.
With the method, it becomes possible to respectively write the same value data on the pixel lines corresponding to the plurality of the scanning signal lines GL1, GL2, . . . GLy in a parallel direction to the data signal lines SL1, SL2, . . . SLx, thereby matching the apparent vertical resolution to the vertical resolution of the image signal.
More specifically, in high vertical resolution driving, which is shown in FIG. 14, the scanning signal lines GL1, GL2, GL3, . . . GLy are individually driven at different timings by the outputs GO1, GO2, . . . Gon. Then, individual data is respectively written on the pixel lines corresponding to the scanning signal lines GL1, GL2, GL3, . . . GLy in a parallel direction to the data signal lines SL1, SL2, . . . SLx, thereby realizing high vertical resolution driving.
On the other hand, in ½ vertical resolution driving, which is shown in FIG. 15, the driving is performed by sequentially driving a set of two adjacent scanning signal lines such as the scanning signal lines GL1 and GL2, scanning signal lines GL3 and GL4 . . . scanning signal lines GLm and GLm+1 (m is an odd number). Then, the same value data is respectively written on the pixel lines corresponding to each of the scanning signal lines in a parallel direction to the data signal lines SL1, SL2, . . . SLx, thereby realizing ½ vertical resolution driving.
The foregoing explanation deals with a general driving method of the scanning signal line driving circuit 62.
However, the conventional matrix image display device has the following problems when an image having low vertical resolution is displayed in an image display device having high vertical resolution.
In the described arrangement, when a plurality of scanning signal lines are driven at the same time, potential variance with respect to pixel lines above and below and adjacent to the plurality of scanning signal lines greatly differ from each other, after data is written to the plurality of pixels thus simultaneously driven. Accordingly, there arises a problem where potential variances differ between the pixels corresponding to the plurality of scanning signal lines GL1 through GLn, which are subject to writing the same value data and are driven by a common coupling capacitor for each pixels.
Namely, as shown in FIG. 16, in the case of driving two scanning signal lines such as the scanning signal lines GL1 and GL2, scanning signal lines GL3 and GL4, and the scanning signal lines GL5 and GL6, the potentials of a pixel line PIXLIN 3 and a pixel line PIXLIN 4 differ as shown in FIG. 17 which are supposed to have the same value. This is due to the difference of the potential variances between a pixel line PIXLIN 2 and a pixel line PIXLIN 5, as the potential variances of these pixel lines affect the pixel line PIXLIN 3 and the pixel line PIXLIN 4. This difference appears as a streaky defect in a parallel direction to the scanning signal lines GL1 through GLn of the image display, thereby decreasing display quality.
Further, when liquid crystal is used as an image display element, inversion of the image signal DAT have to be repeated with a certain period for its reliability, and great potential variance (normally about 10V for example) is occurred before and after the inversion.
Here, FIGS. 18(a) through 18(c) show the methods of inversion. FIG. 18(a) shows a 1H inversion driving which carries out inversion every 1 horizontal period. Further, FIG. 18(b) shows a 1V inversion driving which carries out inversion every 1 vertical period. Further, FIG. 18(c) shows a dot inversion driving which carries out inversion every 1 dot and every 1 vertical period.
Among those three methods, the 1H inversion driving of FIG. 18(a) and the dot inversion driving of FIG. 18(c) are often adopted in terms of display quality. However, the foregoing problem becomes more prominent when the 1H inversion driving and the dot inversion driving are adopted, as those inversions are performed between the adjacent pixel lines in the data signal line direction.